1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device. In particular, the present invention relates to a circuit for controlling a power-source potential of the semiconductor integrated circuit device, and a method of trimming the power-source potential.
2. Description of the Related Art
In a semiconductor integrated circuit device, a specific potential used in the device is often generated by using a charge pump and the like. In a case of a flash memory, for example, a specific potential used for data programming is generated in the device. Such a specific potential is hereinafter referred to as a power-source potential or an internal potential. The internal potential is generated based on a reference potential, and the reference potential may vary between semiconductor chips due to manufacturing variability. It is therefore necessary to fine adjust the internal potential for every semiconductor chip. Such an adjustment of the internal potential is referred to as a “trimming”.
FIG. 1 shows a configuration of a conventional semiconductor integrated circuit device. A charge pump 101 supplies an internal potential V1 to a first node N1. A resistance potential divider 104 is connected to the first node N1. A potential V2 at a second node N2 is determined by the internal potential V1 and a division ratio of the resistance potential divider 104. A comparator 105 makes a comparison between the potential V2 at the second node N2 and a predetermined reference potential VREF. The result of the comparison is fed-back to the charge pump 101. The charge pump 101 outputs the internal potential V1 such that the potential V2 becomes equal to the reference potential VREF.
Here, for example, the reference potential VREF may vary between manufactured semiconductor chips. It is therefore necessary to adjust the division ratio of the resistance potential divider 104 for every manufactured semiconductor chip and hence to equalize the internal potentials V1 with respect to all the semiconductor chips. For the purpose of adjusting (trimming) the division ratio, the semiconductor integrated circuit device is provided with a trimming decoder 103. The trimming decoder 103 decodes a code referred to as a “trimming code” and sets the division ratio of the resistance potential divider 104 to a value corresponding to the trimming code. When the trimming code is changed, the division ratio varies and hence the internal potential V1 also varies. By adjusting the trimming code for every semiconductor chip, it is possible to equalize the internal potentials V1 to a desired value, namely, it is possible to eliminate the influence of the variation of the reference potential VREF.
More specifically, at the time of the trimming, a switch 106 is turned ON by a switch open/close signal SW, and hence the internal potential V1 appears at a pad 107 for use in voltage monitoring. Also, a plurality of kinds of trimming codes are supplied to the trimming decoder 103 from a tester. By switching the trimming code and monitoring the internal potentials V1 output from the pad 107 for use in voltage monitoring, it is possible to determine an optimum trimming code corresponding to a desired internal potential V1. Such the trimming is performed with respect to every manufactured semiconductor chip. The purpose of the trimming is to determine the optimum trimming code for every manufactured semiconductor chip. At a time of a normal operation, the above-mentioned optimum trimming code determined in the trimming is used. As a result, the charge pump 101 of each semiconductor chip operates to output the desired internal potential V1.
According to the above-explained conventional technique, it is necessary to switch the trimming code while monitoring the output potential output from the pad 107, which leads to an increase in a time required for the trimming operation. A technique for making the trimming easy and suppressing the time required for the trimming is disclosed in, for example, Japanese Laid-Open Patent Application (JP-P2002-318265A). According to the technique described in the patent document, a built-in CPU executes the trimming in accordance with a built-in program in a self-sufficient manner.
As another technique for making the trimming easy, a semiconductor device disclosed in Japanese Laid-Open Patent Application (JP-P2002-368113A) is publicly known. FIG. 2 shows a configuration of a trimming circuit (tuning circuit) in the patent document. An internal potential IntVCC is generated by an internal power-source potential generating circuit 201. The level of the internal potential IntVCC varies in accordance with a trimming code (P0-P3) of 4 bits. At the time of the trimming, a built-in signal generating circuit 202 supplies a plurality of trimming codes sequentially to the internal power-source potential generating circuit 201. A comparator 203 makes a comparison between each internal potential IntVCC and a reference potential VR, and outputs a signal φ indicative of a result of the comparison to a memory circuit 204. The output signals φ associated with all of the plurality of trimming codes are stored in the memory circuit 204. By analyzing data φT stored in the memory circuit 204, it is possible to determine an optimum trimming code with which a desired internal potential IntVCC is generated.